1. Field of the Invention
The present invention relates generally to a dynamic memory device, and, more particularly, to a dynamic memory device ensuring an effective application of high and low level of voltages between bit line pairs in stress testing.
2. Description of the Related Art
Dynamic memory devices (or DRAMs) necessitate not merely high speed with large capacity but also high reliability. As measures for improving the reliability, stress testing is made in which stress is applied to the devices before delivery to make clear the defects formed during the manufacturing process. In this stress testing, to make clear the short between the adjacent bit line pairs, which is a typical defectiveness of the memory devices, alternate high and low level of voltages are applied between the adjacent bit line pairs so as to change unfinished defects occurring between the bit line pairs upon the manufacture into finished defects. Operation testing is made after such a stress application, to thereby prevent less reliable defectives from being put on the market.
To externally apply voltages to a bit line pair in the ordinary memory devices, however, high and low level of voltages must be applied to a pair of bit lines selected, by utilizing a write command, through a path which consists of an external terminal, a write amplifier, a data bus and a bit line pair. A large-capacity dynamic memory device comprises a plurality of memory banks each including a plurality of memory blocks, each of which is provided therein with a memory cell array having a plurality of bit line pairs. It is possible in such a case to utilize the operation mode for activating the plurality of memory banks at a time, to thereby externally apply a desired voltage to the bit line pairs of each memory bank at the same time. However, only a single memory block can be selected within the memory bank, and only a single bit line pair can be selected within the memory block.
Therefore, insofar as the function in the ordinary operation is utilized, the stress testing merely allow extremely few bit line pairs of the entire chip to simultaneously be subjected to high and low voltages. Accordingly, an elongated time is required for the stress testing, resulting in a rise of the product testing costs.
In the dynamic memory devices, due to some reasons such as operation testing, a function has hitherto been proposed by which selection is made of a plurality of bit line pairs or all bit line pairs for the connection to the data bus pair. Another function has also been proposed by which a plurality of memory blocks are selected to connect the global data bus pair to the local data bus pairs of the plurality of memory blocks. It is conceivable with the addition of such functions to increase the number of bit line pairs simultaneously subjected to high and low level of voltages in the stress testing, to thereby shorten the stress testing time.
However, as long as the conventional write command is utilized irrespective of use of the above plural bit line pair selection function or plural memory block selection function, it would be impossible to expect for the write amplifier to have a drive ability sufficient to invert all the sense amplifiers connected to the plurality of bit line pairs. The activation of the sense amplifier is needed for the drive of the bit line pairs into sufficiently high and low levels, whereas the existence such a sense amplifier poses an impedance to the case where simultaneous stress is applied to a plurality of bit line pairs in the stress testing.
It is therefore an object of the present invention to provide a memory device having a shortened stress testing time.
It is another object of the present invention to provide a memory device capable of simultaneous application of high and low level of voltages to a plurality of bit line pairs.
In order to achieve the above objects, according to a first aspect of the present invention, upon stress testing mode more bit line pairs than ordinary write mode are commonly connected to a data bus, and a write amplifier applies high and low voltages to the simultaneously connected bit line pairs. Thereafter, at a different timing than an ordinary writing, the sense amplifiers associated with the selected bit line pairs are activated to drive the bit line pair, for the application of sufficient voltage.
In the first aspect, in case of a configuration where the data bus includes a global data bus and a plurality of local data buses connectable thereto, and the bit line pairs are selectively connected to the local data bus, in the stress testing mode more local data buses than the ordinary write mode are placed in connection with the global data bus. Then, the write amplifier is connected to the global data bus.
In the ordinary write mode, after the drive of the word lines the sense amplifier is activated to drive the bit line pairs. The write amplifier then drives the bit line pairs so that write data are written into the memory cell. Thus, the write amplifier needs to invert the already activated sense amplifier connected to the selected bit lines. According to the first aspect of the present invention, as opposed to this, in the stress testing mode, after the drive of the bit lines by the write amplifier while the sense amplifiers are not activated, the sense amplifiers are driven, so that there is no need to invert the plurality of sense amplifiers by the write amplifier, enabling the write amplifier to drive a plurality of bit line pairs.
In a more preferred embodiment, a stress testing mode signal is externally fed as a specific signal or command to the memory device, and a stress application data signal is fed through the data input/output terminal so that a plurality of bit line pairs more than the ordinary mode are connected to the data bus to drive the bit line pairs by the write amplifier into high and low levels. At the timing after the elapse of a certain period of time, a sense amplifier activation timing signal is externally fed to activate the sense amplifiers corresponding to the selected bit line pairs so as to drive the bit line pairs into high and low levels. The above data signal and sense amplifier activation timing signal may specially be generated by an internal circuit.
According to the present invention described above, the existing write amplifier can be utilized for simultaneous stress application to a plurality of bit line pairs so that the stress testing time can be reduced.
To attain the above objects, according to a second aspect of the present invention there is provided a dynamic memory device having a plurality of bit line pairs, a plurality of word lines, and a plurality of memory cells provided at the intersection thereof, the dynamic memory device comprising: a data bus to which a write amplifier is connected; and sense amplifiers provided to each of the bit line pairs for amplifying voltage between the bit line pair; wherein in a stress testing mode, a plurality of bit line pairs are commonly connected to the data bus, the write amplifier applies high and low level of voltages to the commonly connected bit line pairs, thereafter the sense amplifiers associated with the selected bit line pairs are activated.